Implementation of Memory Subsystem of Cycle-Accurate Application-Level Simulator of the Elbrus Microprocessors
https://doi.org/10.15514/ISPRAS-2020-32(2)-6
Abstract
Performance characteristics of any modern microprocessor largely depend on its memory subsystem. Naturally, the memory subsystem software model is an important component of the cycle-accurate simulator, and its validity and quality have high impact on the overall accuracy of the simulation. In this paper the cycle-accurate application-level simulator of the Elbrus microprocessor family is introduced. The structure of the cycle-accurate simulator is briefly explained. After that the software model of memory subsystem and its integration as a part of the cycle-accurate application-level simulator are described. We evaluate accuracy of the application-level cycle-accurate simulator on the SPEC CPU2006 benchmark and analyze the simulation errors. Finally, a brief comparison of different Elbrus architecture simulators is given.
About the Authors
Pavel Alexeevitch POROSHIN
INEUM
Russian Federation
Software engineer
Russian Federation
Software engineer
Dmitry Valerievich ZNAMENSKIY
MCST
Russian Federation
Russian Federation
Alexey Nikolaevitch MESHKOV
INEUM, MCST
Russian Federation
PhD, chief of department at MCST
Russian Federation
PhD, chief of department at MCST
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Review
For citations:
POROSHIN P.A., ZNAMENSKIY D.V., MESHKOV A.N. Implementation of Memory Subsystem of Cycle-Accurate Application-Level Simulator of the Elbrus Microprocessors. Proceedings of the Institute for System Programming of the RAS (Proceedings of ISP RAS). 2020;32(2):61-80. https://doi.org/10.15514/ISPRAS-2020-32(2)-6
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