Data Layout Optimization for the LCC Compiler
https://doi.org/10.15514/ISPRAS-2021-33(3)-4
Abstract
In this research-in-progress report, we propose a novel approach to unified cache usage analysis for implementing data layout optimizations in the LCC compiler for the Elbrus and SPARC architectures. The approach consists of three parts. The first part is generalizing two methods of estimating cache miss amount and choosing more applicable one in the compiler. The second part is finding an applicable solution for the problem of cache miss amount minimization. The third part is implementing this analysis in the compiler and using analysis results for data layout transformations.
About the Authors
Viktor SHAMPAROV
MCST, Moscow Institute of Physics and Technology
Russian Federation
Russian Federation
PhD student at MIPT, software engineer at MCST
Murad NEIMAN-ZADE
Moscow Institute of Physics and Technology
Russian Federation
Russian Federation
PhD in mathematics, associated professor
References
1. В.Е. Шампаров, А.Л. Маркин. Механизм оптимизации Structure Splitting в составе компилятора для микропроцессоров Эльбрус. Программная инженерия, том 12, no. 2, 2021 г., стр. 82-88 / V. E. Shamparov and A. L. Markin. Structure splitting for elbrus processor compiler. Software Engineering, vol. 12, no. 2, 2021, pp. 82-88 (in Russian).
2. C. Lattner. Macroscopic Data Structure Analysis and Optimization. Ph.D. dissertation, Computer Science Dept., University of Illinois at Urbana-Champaign, 2005, 225 p.
3. C. Haine. Estimation d'efficacité et restructuration automatisées de noyaux de calcul. (Kernel optimization by layout restructuring). Ph.D. dissertation, University of Bordeaux, France, 2017, 114 p.
4. M. Hagog and C. Tice. Cache aware data layout reorganization optimization in gcc. In Proc. of the GCC Developers’ Summit, 2005, pp. 69-92.
5. S. Ghosh, M. Martonosi, and S. Malik. Cache miss equations: A compiler framework for analyzing and tuning memory behavior. ACM Transactions on Programming Languages and Systems, vol. 21, no. 4, 1999, pp. 703-746.
6. B.B. Fraguela, R. Doallo, and E.L. Zapata. Probabilistic miss equations: Evaluating memory hierarchy performance. IEEE Transactions on Computers, vol. 52, no. 3, 2003, pp. 321-336
7. D. Andrade. Systematic analysis of the cache behavior of irregular codes. Ph.D. dissertation, Department of Electronics and Systems, University of A Coruña, Spain, 2007, 165 p.
8. M. Kowarschik and C. Weiß. An Overview of Cache Optimization Techniques and Cache-Aware Numerical Algorithms. Lecture Notes in Computer Science, vol, 2625, 2003, pp. 213-232.
Review
For citations:
SHAMPAROV V., NEIMAN-ZADE M. Data Layout Optimization for the LCC Compiler. Proceedings of the Institute for System Programming of the RAS (Proceedings of ISP RAS). 2021;33(3):51-60. https://doi.org/10.15514/ISPRAS-2021-33(3)-4
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