Evaluation of Hardware Data Compression in Interprocessor Links of Elbrus Processors
https://doi.org/10.15514/ISPRAS-2022-34(1)-4
Abstract
The tendency to increase core count in modern processor systems leads to a higher strain on memory subsystem. In particular, one of the most critical points in terms of throughput is interprocessor links, where bandwidth is significantly less than in processor data buses. Hardware data compression can be considered as one of the ways to increase throughput in interprocessor links, as it allows to decrease the amount of information transmitted over the links. This paper presents the evaluation of hardware data compression in interprocessor links of Elbrus processors. BΔI*-HL compression algorithm is chosen for the evaluation. The results are obtained of FPGA prototype of “Elbrus-16C” processor for the tasks of SPEC CPU2000 benchmark suite. They show that by using hardware data compression 38,0% of all data packets were compressed and that the amount of information transmitted overall has decreased by 13,4%. These results demonstrate that the use of hardware data compression in interprocessor links of Elbrus processors is justified and has potential to significantly increase memory subsystem performance.
About the Author
Alexander Viktorovich SURCHENKO
АО "МЦСТ", Московский физико-технический институт
Russian Federation
Russian Federation
PhD student in MIPT, Senior Engineer at JSC «MCST».
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Review
For citations:
SURCHENKO A.V. Evaluation of Hardware Data Compression in Interprocessor Links of Elbrus Processors. Proceedings of the Institute for System Programming of the RAS (Proceedings of ISP RAS). 2022;34(1):49-58. (In Russ.) https://doi.org/10.15514/ISPRAS-2022-34(1)-4
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