An Approach to Test Program Generation for Memory Coherence Verification of “Elbrus” Microprocessors
https://doi.org/10.15514/ISPRAS-2022-34(2)-1
Abstract
One of the key aspects of the correctness of the memory subsystem of a microprocessor is its functioning in accordance with the memory coherence protocol. This article presents an approach to test program generation for memory coherence verification of “Elbrus” microprocessors. Requirements for memory coherence tests are considered. The memory map structure allowing to describe the memory areas used in tests and the types of accesses to these areas in a flexible way is presented. The method of test program generation based on the memory map structure is described. The method of automatic memory map generation is proposed. Generated tests have been used for verification of RTL models and FPGA-based prototypes.
About the Authors
Vladimir Andreevich AGAFONOV
Moscow Institute of Physics and Technology (National Research University),
MCST
Russian Federation
Russian Federation
Lead engineer of the sector of system-level verification ("verification and modeling" department at JSC MCST), postgraduate student at MIPT
Pavel Viktorovich FROLOV
Moscow Institute of Physics and Technology (National Research University),
MCST,
INEUM
Russian Federation
Russian Federation
Head of the sector of system-level verification ("verification and modeling" department at JSC MCST)
Alexey Nikolaevich MESHKOV
MCST,
INEUM
Russian Federation
Russian Federation
Ph.D. in Technology, head of "verification and modeling" department at JSC MCST
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Review
For citations:
AGAFONOV V.A., FROLOV P.V., MESHKOV A.N. An Approach to Test Program Generation for Memory Coherence Verification of “Elbrus” Microprocessors. Proceedings of the Institute for System Programming of the RAS (Proceedings of ISP RAS). 2022;34(2):7-16. https://doi.org/10.15514/ISPRAS-2022-34(2)-1
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