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The Open System for Storing and Processing of a Dataset of Combinational Circuits

https://doi.org/10.15514/ISPRAS-2022-35(5)-6

Abstract

This paper presents an open-source software for generation, storage, and analysis of combinational circuits. The previously created methods for generating combinational circuits have been optimized, and a dataset has been formed. The generation of combinational circuits is carried out on various devices. The application implements the possibility to combine the generated datasets into a single storage (Synology Drive), as well as analyze the fault tolerance of combinational circuits using various methods for their evaluation. New possible methods for assessing combinational circuits’ reliability using machine learning are proposed.

About the Authors

Danil Aleksandrovich MIACHIN
HSE University
Russian Federation

Student from the HSE University. Research interests: machine learning, CAD development.



Viktoriia Pavlovna PUGACH
HSE University
Russian Federation

Student from the HSE University. Research interests: machine learning, CAD development.



Stepan Sergeevich AVDEIUK
HSE University
Russian Federation

Student from the HSE University. Research interests: machine learning, CAD development.



Vladimir Viktorovich ZUNIN
HSE University
Russian Federation

Postgraduate student from the HSE University. Research interests: machine learning, CAD systems.



Aleksandr Yur’yevich ROMANOV
HSE University
Russian Federation

PhD in Technical Sciences, Associate Professor, Head of the Laboratory of Computer-Aided Design Systems at the HSE University. Research interests: networks-on-chip, systems-on-chip, machine learning, CAD systems.



References

1. Harris S. L., Harris D. M. Digital Design and Computer Architecture: RISC-V Edition. Morgan Kaufmann, 2021. 592 p.

2. Roy S., Tilak C. T. On Synthesis of Combinational Logic Circuits. International Journal of Computer Applications, vol. 127, no. 1, 2015, pp. 21–26. DOI: 10.5120/IJCA2015906311.

3. Han J., Chen H., Boykin E., Fortes J. Reliability evaluation of logic circuits using probabilistic gate models. Microelectronics Reliability, vol. 51, no. 2, 2011, pp. 468–476. DOI: 10.1016/j.microrel.2010.07.154.

4. Choudhury M. R., Mohanram K. Reliability Analysis of Logic Circuits. IIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 28, no. 3, 2009, pp. 392–405. DOI: 10.1109/TCAD.2009.2012530.

5. Стемпковский А. Л., Тельпухов Д. В., Соловьев Р. А., Тельпухова Н. В. Исследование вероятностных методов оценки логической уязвимости комбинационных схем. Проблемы разработки перспективных микро- и наноэлектронных схем, №4, 2016, сс. 121-126. / Stempkovskiy A.L., Telpukhov D.V., Soloviev R.A., Telpukhova N.V. Probabilistic methods for reliability evaluation of combinational Circuits. Problems of Perspective Micro- and Nanoelectronic Systems Development, no. 4, 2016, pp. 121-126 (in Russian).

6. Тельпухов Д. В., Соловьев Р. А., Тельпухова Н. В., Щелоков А. Н. Оценка параметра логической чувствительности комбинационной схемы к однократным ошибкам с помощью вероятностных методов. Известия ЮФУ. Технические науки, №7, 2016, сс. 149–158. DOI: 10.18522/2311-3103-2016-7-149158. / Telpukhov D.V., Soloviev R. A., Telpukhova N. V., Schelokov A.N. Ocenka parametra logicheskoj chuvstvitel'nosti kombinacionnoj shemy k odnokratnym oshibkam s pomoshh'ju verojatnostnyh metodov. Izvestija JuFU. Tehnicheskie nauki, no. 7, 2016, pp. 149-158. DOI: 10.18522/2311-3103-2016-7-149158 (in Russian).

7. Стемпковский А. Л., Тельпухов Д. В., Соловьев Р. А., Мячиков М. В., and Тельпухова Н. В., “Разработка технологически независимых метрик для оценки маскирующих свойств логических схем,” Вычислительные технологии, том 21, №2, 2016, сс. 53–62. / Stempkovskiy A.L., Telpukhov D.V., Soloviev R.A., Myachikov M. V., Telpukhova N. V. The development of technology-independent metrics for evaluation of the masking properties of logic, vol. 21, no. 2, 2016, pp. 53-62.

8. Icarus Verilog, Available at: https://github.com/steveicarus/iverilog, accessed 27.07.2023.

9. NI Multisim Circuit Design Suite, Available at: https://www.studica.com/NI-Circuit-Design-Suite-Student-Edition-Download, accessed 27.07.2023.

10. Logicly, Available at: https://logic.ly/, accessed 27.07.2023.

11. CAD_Combinational_Circuits, Available at: https://github.com/RomeoMe5/CAD_Combinational_Circuits, accessed 27.07.2023.

12. Json.NET – Newtonsoft, Available at: https://www.newtonsoft.com/json, accessed 27.07.2023.

13. Yosys Open Synthesis Suite, Available at: https://yosyshq.net/yosys/, accessed 27.07.2023.

14. Synology Drive API, Available at: https://github.com/zbjdonald/synology-drive-api, accessed 27.07.2023.

15. Graphviz, Available at: https://graphviz.org/, accessed 28.07.2023.

16. Zunin V. V., Romanov A. Y., Solovyev R. A. Developing Methods for Combinational Circuit Generation. In Proceedings - 2022 International Russian Automation Conference (RusAutoCon), 2022, pp. 842–846. DOI: 10.1109/RUSAUTOCON54946.2022.9896390.

17. Banzhaf W., Nordin P., Keller R., Francone F. Genetic programming: an introduction on the automatic evolution of computer programs and its applications. Morgan Kaufmann Publishers, 1998.

18. Nadezhda - Reliability Enhancement Logic tool for Integrated Circuits design, Available at: https://alphachip-tools.ru/nadezhda.php, accessed 27.07.2023.

19. CMake, Available at: https://cmake.org/, accessed 28.06.2023.

20. Chen T., Guestrin C. XGBoost. In Proceedings of the 22nd ACM SIGKDD International Conference on Knowledge Discovery and Data Mining, 2016, pp. 785–794. DOI: 10.1145/2939672.2939785.

21. Wu Z., Pan S., Chen F., Long G., Zhang C., Yu P. S. A Comprehensive Survey on Graph Neural Networks. IEEE Trans. Neural Networks Learn. Syst., vol. 32, no. 1, 2021, pp. 4–24, DOI: 10.1109/TNNLS.2020.2978386.

22. Зунин В.В., Романов А.Ю. Intel OpenVINO™ Toolkit: анализ производительности выполнения генеративно-состязательных нейронных сетей. Проблемы разработки перспективных микро- и наноэлектронных систем (МЭС), выпуск 2, 2021, сс. 83–90. DOI: 10.31114/2078-7707-2021-2-83-90. / Zunin V.V., Romanov A. Y. Intel OpenVINO™ Toolkit: Performance Analysis of Generative Adversarial Neural Networks. Problems of Perspective Micro- and Nanoelectronic Systems Development, issue 2, 2021, pp. 83-90. DOI: 10.31114/2078-7707-2021-2-83-90.

23. Otter D. W., Medina J. R., Kalita J. K. A Survey of the Usages of Deep Learning for Natural Language Processing. IEEE Trans. NEURAL NETWORKS Learn. Syst., vol. 32, no. 2, 2021, DOI: 10.1109/TNNLS.2020.2979670.

24. Kamath U., Liu J., Whitaker J. Deep Learning for NLP and Speech Recognition. Springer International Publishing, 2019. DOI: 10.1007/978-3-030-14596-5.

25. Romanov A., Kozlova E., Lomotin K. Application of NLP Algorithms: Automatic Text Classifier Tool. In Communications in Computer and Information Science, vol. 859, 2018, pp. 310–323. DOI: 10.1007/978-3-030-02846-6_25.

26. Tixier A. J. P., Nikolentzos G., Meladianos P., Vazirgiannis M. Graph Classification with 2D Convolutional Neural Networks. Lecture Notes in Computer Science, vol. 11731, 2017, pp. 578–593, DOI: 10.1007/978-3-030-30493-5_54.


Review

For citations:


MIACHIN D.A., PUGACH V.P., AVDEIUK S.S., ZUNIN V.V., ROMANOV A.Yu. The Open System for Storing and Processing of a Dataset of Combinational Circuits. Proceedings of the Institute for System Programming of the RAS (Proceedings of ISP RAS). 2023;35(5):81-90. https://doi.org/10.15514/ISPRAS-2022-35(5)-6



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ISSN 2079-8156 (Print)
ISSN 2220-6426 (Online)