Parallel Implementation of the Algorithm for Correction of Antenna Rule Violations in OpenLane Design Flow
https://doi.org/10.15514/ISPRAS-2023-35(6)-12
Abstract
The open IC design flow OpenLane make available the RTL-to-GDS design flow to be implemented, but still some tasks remain unsolved. An example of such task is the correction of antenna rules violations. The detection tools for this procedure are the part of the OpenLane flow but it does not contain any tools for avoiding them. In this article the software is presented that has been developed and allows to avoid violations of antenna rules based on input data in the form of LEF file with information about the standard cell library and DEF file with information about the placement and routing of the design. A parallel implementation is also described; we show the results of more than 60% gain in time with using parallel version in comparison with sequential version. The article describes both the developed algorithm and the software built on its basis, the capability of embedding into an open OpenLane flow, and an example of embedding script code. The use of the developed software makes it possible to correct a significant part of antenna rules violations, thereby increasing the yield.
Supporting agencies: This work was carried out with the financial assistance of the Ministry of Education and Science in the framework of state task FSMR-2023-0008 (Development of a methodology for prototyping electronic component base at domestic microelectronic production facilities on the basis of MPW service).
About the Authors
Dmitriy Aleksandrovich BULAKH
National Research University of Electronic Technology
Russian Federation
Russian Federation
Candidate of Technical Sciences, Assistant Professor at the Institute of Integrated Electronics. Research interests: VLSI EDA data simulation, processing and visualization algorithms.
Andray Vladimirovich KORSHUNOV
National Research University of Electronic Technology
Russian Federation
Russian Federation
Candidate of Technical Sciences, Assistant Professor at the Institute of Integrated Electronics. Research interests: research and development of design methods for energy-efficient VLSI and SoCs.
References
1. M. Shalan and T. Edwards, "Building OpenLANE: A 130nm OpenROAD-based Tapeout- Proven Flow : Invited Paper," 2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD), San Diego, CA, USA, 2020, pp. 1-6.
2. Зыков А.В., Ильясов Р.Ф. Анализ работы программных инструментов с открытым исходным кодом OpenLANE для разработки микросхем // Проблемы разработки перспективных микро- и наноэлектронных систем (МЭС). 2022. Выпуск 4. С. 87-92. doi:10.31114/2078-7707-2022-4-87-92
3. T. Ajayi, V. A. Chhabria, M. Fogaça, S. Hashemi, A. Hosny, A. B. Kahng, M. Kim, J. Lee, U. Mallappa, M. Neseem, G. Pradipta, S. Reda, M. Saligane, S. S. Sapatnekar, C. Sechen, M. Shalan, W. Swartz, L. Wang, Z. Wang, M. Woo and B. Xu, "Toward an Open-Source Digital Flow: First Learnings from the OpenROAD Project," Proc. ACM/IEEE Design Automation Conference, 2019, pp. 76:1-76:4. (Invited Paper)
4. S. Reda, "Overview of the OpenROAD Digital Design Flow from RTL to GDS," 2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), Hsinchu, Taiwan, 2020, pp. 1-1, doi: 10.1109/VLSI-DAT49148.2020.9196319.
5. Lin, Chung-Wei & Tsai, Ming-Chao & Lee, Kuang-Yao & Chen, Tai-Chen & Wang, Ting-Chi & Chang, Yao-Wen. (2007). Recent Research and Emerging Challenges in Physical Design for Manufacturability/Reliability. Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. 238-243. 10.1109/ASPDAC.2007.357992.
6. Кравченко, В. САПР компании Synopsys. Основные средства и возможности / В. Кравченко, Д. Радченко // ЭЛЕКТРОНИКА: Наука, Технология, Бизнес. — Выпуск 5. — 2003. — С. 31-33.
7. K. Herman, M. Montanares and J. Marin, "Design and Implementation of Integrated Circuits Using Open Source Tools and SKY130 Free PDK," 2023 30th International Conference on Mixed Design of Integrated Circuits and System (MIXDES), Kraków, Poland, 2023, pp. 105-110, doi: 10.23919/MIXDES58562.2023.10203216.
8. Tsai, Chia-Chun & Hsu, Feng-Tzu & Kuo, Chung-Chieh & Wu, Jan-Ou & Lee, Trong-Yen. (2008). X-clock tree construction for antenna avoidance. International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT. 2248 - 2251. 10.1109/ICSICT.2008.4735038.
9. Cho, Minsik & Mitra, Joydeep & Pan, David. (2008). Manufacturability Aware Routing. 10.1201/9781420013481.ch38.
10. Информация об авторах / Information
Review
For citations:
BULAKH D.A., KORSHUNOV A.V. Parallel Implementation of the Algorithm for Correction of Antenna Rule Violations in OpenLane Design Flow. Proceedings of the Institute for System Programming of the RAS (Proceedings of ISP RAS). 2023;35(6):189-198. (In Russ.) https://doi.org/10.15514/ISPRAS-2023-35(6)-12
Email this article 