Architecture for Time Synchronization in an onboard SpaceWire Network of ARINC 653 Nodes
https://doi.org/10.15514/ISPRAS-2025-37(4)-15
Abstract
In this paper we present the architecture for time synchronization in an onboard network. The architecture is specific to SpaceWire protocol and is based on mechanism of broadcast codes introduced in ECSS-E-ST-50-12C standard. We examine synchronization of real time clocks as well as synchronization of ARINC 653 node schedulers. We discuss the modification to ARINC 653 Interrupt Services required for time synchronization to operate. Achieved precision of synchronization is no worse than 5 ms.
Keywords
real-time operating system,
network stack,
distributed systems,
ARINC 653,
SpaceWire,
time synchronization.
Supporting agencies: All the members of the hard real-time operating systems development and verification group at ISP RAS for their support and ideas. Savva Mitrofanov and Rustam Subkhankulov for their hands-on contributions to the result of this paper. RC Module for their invaluable technical support regarding the internals of SpaceWire hardware.
About the Authors
Vladislav Vladimirovich ALEINIK
Institute for System Programming of the Russian Academy of Sciences
Russian Federation
Russian Federation
Employee of the department of Programming Technologies of the Ivannikov Institute for System Programming of the Russian Academy of Sciences; PhD student at Moscow Institute of Physics and Technology. Research interests: real-time operating systems, network stack architecture, SpaceWire networks.
Ilya Vladislavovich RUSETSKIY
Institute for System Programming of the Russian Academy of Sciences
Russian Federation
Russian Federation
Employee of the department of Programming Technologies of the Ivannikov Institute for System Programming of the Russian Academy of Sciences; graduate master student at Moscow State University. Research interests: real-time operating systems, distributed systems, network stack verification.
Vitaliy Yurievich CHEPTSOV
Institute for System Programming of the Russian Academy of Sciences
Russian Federation
Russian Federation
OS architect at ISP RAS; author of OpenCore project; contributor of Tianocore EDK II and UEFITool. Research interests: onboard hard-real time operating systems, security of general-purpose operating systems.
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Review
For citations:
ALEINIK V.V., RUSETSKIY I.V., CHEPTSOV V.Yu. Architecture for Time Synchronization in an onboard SpaceWire Network of ARINC 653 Nodes. Proceedings of the Institute for System Programming of the RAS (Proceedings of ISP RAS). 2025;37(4):7-16. https://doi.org/10.15514/ISPRAS-2025-37(4)-15
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