Application of SVAN Static Analysis Tool on Open RTL Benchmarks
https://doi.org/10.15514/ISPRAS-2025-37(5)-10
Abstract
The article presents an experimental evaluation of SVAN, a static analysis tool designed for functional verification of RTL models written in Verilog and SystemVerilog. The research addresses the growing need for reliable domestic EDA tools, particularly in light of restrictions on proprietary solutions. SVAN’s architecture integrates formal methods and heuristic approaches to detect a wide range of errors, including syntactic issues, coding style violations, logical inconsistencies, and security vulnerabilities. Empirical testing on open-source hardware benchmarks demonstrates SVAN’s superior effectiveness compared to Synopsys VCS and Verilator, with a 73% broader error detection spectrum and 25-23% higher error identification rate, respectively. Key advantages of SVAN include high analysis accuracy and detailed error classification. However, limitations such as reduced flexibility in handling mixed-language designs highlight areas for future improvement. The study underscores SVAN’s potential as a competitive tool for static verification in electronic design automation.
Keywords
static analysis,
RTL,
SVAN,
Verilog,
SystemVerilog,
functional verification,
error detection,
open-source benchmarks.
Supporting agencies: The project is supported by the Ministry of Industry and Trade of the Russian Federation within the R&D project “Development of a static analysis system for a hardware description language”, code “CAD-Analysis” (as part of the R&D project “CAD microelectronics”, the main contractor is JSC “ISTC MIET”).
About the Authors
Sophia M. PANOVA
Ivannikov Institute for System Programming of the Russian Academy of Sciences,
Plekhanov Russian University of Economics
Russian Federation
Russian Federation
Laboratory assistant at the Software Engineering Department of the Ivannikov Institute for System Programming of the Russian Academy of Sciences (ISP RAS). Her research interests include digital hardware design, static analysis, and functional verification.
Sergey A. SMOLOV
Ivannikov Institute for System Programming of the Russian Academy of Sciences,
Plekhanov Russian University of Economics
Russian Federation
Russian Federation
Researcher at the Software Engineering Department of Ivannikov Institute for System Programming of the Russian Academy of Sciences (ISP RAS), senior researcher at the Heterogeneous Computing Systems research lab of Plekhanov RUE. His research interests include digital hardware design automation, verification and testing.
Marina М. VOLKOVA
Ivannikov Institute for System Programming of the Russian Academy of Sciences,
Plekhanov Russian University of Economics
Russian Federation
Russian Federation
Laboratory assistant at the Software Engineering Department of Ivannikov Institute for System Programming of the Russian Academy of Sciences (ISP RAS). Her research interests include machine learning, data analysis, methods of static analysis and verification.
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Review
For citations:
PANOVA S.M., SMOLOV S.A., VOLKOVA M.М. Application of SVAN Static Analysis Tool on Open RTL Benchmarks. Proceedings of the Institute for System Programming of the RAS (Proceedings of ISP RAS). 2025;37(5):131-142. (In Russ.) https://doi.org/10.15514/ISPRAS-2025-37(5)-10
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