Static Analysis of Power Intent in Integrated Circuits
Arman Vagharshakovich YEGHIAZARYAN,
Yan Andreevich CHURKIN,
Ilya Igorevich CHERNYAVSKIKH,
Artem Mikhailovich KOTSYNYAK,
Konstantin Nikolaevich KITAEV,
Ruben Arturovich BUCHATSKIY,
Alexander Sergeevich KAMKIN,
Andrey Vladimirovich KORSHUNOV,
Alexey Leonidovich PEREVERZEV https://doi.org/10.15514/ISPRAS-2026-38(3)-3
Abstract
With the increasing number of electrical components and integrated circuits’ physical size reduction, organizing the energy-efficient operation of digital hardware has become significantly more complex. Traditional hardware description languages Verilog/SystemVerilog and VHDL lack the means for effectively defining and optimizing the description of the power intent. To address this issue, the IEEE 1801 standard introduced the Unified Power Format (UPF), which allows for the formalization of the power management structure and rules in digital systems. However, most modern EDA tools that support the interpretation of UPF descriptions are commercial and often exhibit deviations from the standard, whereas non-commercial tools significantly lag behind their commercial counterparts in terms of language command support and rarely include power intent analysis capabilities. This paper presents a tool for interpreting UPF descriptions and performing static analysis of the power intent model that fully supports the IEEE 1801-2018 standard.
Keywords
power intent,
Unified Power Format,
UPF,
Tcl,
static analysis,
hardware description language,
Verilog,
SystemVerilog,
integrated circuit,
EDA,
AST,
SVAN.
Supporting agencies: The project is supported by the Ministry of Industry and Trade of the Russian Federation within the R&D project “Development of a static analysis system for a hardware description language”, code “SAPR-Analiz” (as part of the R&D project “SAPR mikroelektronika”, the main contractor is JSC “ISTC MIET”).
About the Authors
Arman Vagharshakovich YEGHIAZARYAN
Ivannikov Institute for System Programming of the Russian Academy of Sciences,
Moscow Institute of Physics and Technology
Russian Federation
Russian Federation
Postgraduate student at MIPT, research assistant at Compiler Technology department of ISP RAS. Research interests: static analysis, compiler technologies, optimizations.
Yan Andreevich CHURKIN
Ivannikov Institute for System Programming of the Russian Academy of Sciences
Russian Federation
Russian Federation
Researcher at Compiler Technology department of ISP RAS. Research interests: static analysis, compiler technologies, optimizations, hardware description languages.
Ilya Igorevich CHERNYAVSKIKH
Ivannikov Institute for System Programming of the Russian Academy of Sciences, HSE University
Russian Federation
Russian Federation
Undergraduate student of at the NRU HSE, laboratory assistant at Programming Technologies department of ISP RAS. Research interests: static analysis, verification, digital hardware design.
Artem Mikhailovich KOTSYNYAK
Ivannikov Institute for System Programming of the Russian Academy of Sciences
Russian Federation
Russian Federation
Researcher at Software Engineering department of ISP RAS. Research interests: formal methods, compiler technologies, models of computation, programming languages.
Konstantin Nikolaevich KITAEV
Moscow Institute of Physics and Technology
Russian Federation
Russian Federation
Master's student at MIPT. Research interests: static analysis, compiler technologies, optimizations.
Ruben Arturovich BUCHATSKIY
Ivannikov Institute for System Programming of the Russian Academy of Sciences
Russian Federation
Russian Federation
Cand. Sci. (Tech.), Senior researcher at Compiler Technology department of ISP RAS. Research interests: static analysis, compiler technologies, optimizations.
Alexander Sergeevich KAMKIN
Ivannikov Institute for System Programming of the Russian Academy of Sciences,
Russian Federation
Russian Federation
Cand. Sci. (Phys.-Math.), leading researcher at Software Engineering department of ISP RAS, leading researcher at Plekhanov Russian University of Economics. Research interests: formal methods, synthesis and verification of digital hardware, and heterogeneous computer systems.
Andrey Vladimirovich KORSHUNOV
JSC "International Scientific and Technological Center of MIET"
Russian Federation
Russian Federation
Cand. Sci. (Tech.), projects lead, JSC "ISTC MIET". Research interests include methods and tools for automated design of microelectronics products, including very large-scale integrated circuits (VLSI) and systems-on-chip (SoC). Key research areas in recent years include the design of VLSI and SoC power networks, energy-efficient design, the development of design tools for photomask production, and automated design technologies for advanced electronic components.
Alexey Leonidovich PEREVERZEV
JSC "International Scientific and Technological Center of MIET"
Russian Federation
Russian Federation
Dr. Sci. (Tech.), First Deputy General Director, JSC "ISTC MIET". The main area of scientific activity: design, analysis and experimental research of information and control systems with the aim of improving their technical characteristics, including the research and development of complex functional blocks, structural and architectural solutions, digital signal processing algorithms and methods for their technical implementation.
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Review
For citations:
YEGHIAZARYAN A.V., CHURKIN Ya.A., CHERNYAVSKIKH I.I., KOTSYNYAK A.M., KITAEV K.N., BUCHATSKIY R.A., KAMKIN A.S., KORSHUNOV A.V., PEREVERZEV A.L. Static Analysis of Power Intent in Integrated Circuits. Proceedings of the Institute for System Programming of the RAS (Proceedings of ISP RAS). 2026;38(3):45-70. (In Russ.) https://doi.org/10.15514/ISPRAS-2026-38(3)-3
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