Simulation-based Verification of System-on-Chip Bus Controllers

Abstract

The paper presents an approach to verification of commutation components of Systems-on-Chip. The core idea is to verify bus controllers and supporting interface parts connected to a reference model at unit-level. The reference model in the approach is suggested to be written in SystemC so that to be easily adjusted to the required bus parameters. The in-house prototype implementing the approach has been applied to the verification of a Verilog model of Wishbone controller. There is a possibility to extend the approach to support other busses and protocols by development of the interface library.