An approach to Direct Memory Access module verification
https://doi.org/10.15514/ISPRAS-2015-27(3)-10
Abstract
A method of direct memory access subsystem verification used for “Elbrus” series microprocessors has been described. A peripheral controller imitator has been developed in order to reduce verification overhead. The model of imitator has been included into the functional machine simulator. A pseudorandom test generator for verification of the direct memory access subsystem has been based on the simulator.
About the Authors
V. . Kutsevol
ZAO MCST
Russian Federation
Russian Federation
A. . Meshkov
ZAO MCST
Russian Federation
Russian Federation
M. . Ryzhov
ZAO MCST
Russian Federation
Russian Federation
P. . Frolov
ZAO MCST
Russian Federation
Russian Federation
References
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Review
For citations:
Kutsevol V., Meshkov A., Ryzhov M., Frolov P. An approach to Direct Memory Access module verification. Proceedings of the Institute for System Programming of the RAS (Proceedings of ISP RAS). 2015;27(3):139-148. (In Russ.) https://doi.org/10.15514/ISPRAS-2015-27(3)-10
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