Preview

Proceedings of the Institute for System Programming of the RAS (Proceedings of ISP RAS)

Advanced search

Instrumentation and optimization of transactional sections execution in multithreaded programs

https://doi.org/10.15514/ISPRAS-2015-27(6)-9

Abstract

In this paper, we investigate efficiency of software transactional memory implementation in GCC compiler. The authors propose software tools for instrumentation to profiling programs with software transactional memory, and describe the method of reducing false conflicts. The method performs the tuning of transactional memory parameters value in GCC implementation (libitm runtime-library) by using the profiling results (profile-guided optimization). The static instrumentation allows to optimize dynamic properties of execution transactional sections. The efficiency of reducing false conflicts is investigated on the STAMP benchmarks.

About the Authors

I. . Kulagin
SibSUTIS
Russian Federation


M. . Kurnosov
ETU
Russian Federation


References

1. M. Herlihy, N. Shavit. The Art of Multiprocessor Programming. Morgan Kaufmann Publishers Inc., San Francisco, CA, USA, 2008.

2. Hendler D., Shavit N., Yerushalmi L. A scalable lock-free stack algorithm // Proceedings of the sixteenth annual ACM symposium on Parallelism in algorithms and architectures. SPAA ’04. 2004. P. 206–215.

3. Kuznetsov S.D. Transaktsionnaya pamat. [Transactional memory]. http://citforum.ru/programming/digest/transactional_memory/. (in Russian).

4. N. Shavit, D. Touitou. Software Transactional Memory. In PODC’95: Proceedings of the fourteenth annual ACM symposium on Principles of distributed computing, New York, NY, USA, Aug. 1995. ACM, 204–213.

5. Pascal Felber, Christof Fetzer, Patrick Marlier, and Torvald Riegel, Time-based Software Transactional Memory, IEEE Transactions on Parallel and Distributed Systems, Volume 21, Issue 12, pp. 1793-1807, December 2010.

6. Torvald Riegel, Pascal Felber, and Christof Fetzer. A Lazy Snapshot Algorithm with Eager Validation, 20th International Symposium on Distributed Computing (DISC), 2006.

7. Victor Luchango, Jens Maurer, Mark Moir. Transactional memory for C++ [PDF]. http://www.open-std.org/jtc1/sc22/wg21/docs/papers/2013/n3718.pdf

8. Rochester Software Transactional Memory Runtime. Project web site [HTML]. www.cs.rochester.edu/research/synchronization/rstm/.

9. Michael F. Spear, Luke Dalessandro, Virendra J. Marathe, and Michael L. Scott. A comprehensive strategy for contention management in software transactional memory. In PPoPP ’09: Proc. 14th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, February 2009, P ¬– 141-150.

10. Kevin E. Moore, Jayaram Bobba, Michelle J. Moravan, Mark D. Hill, and David A. Wood. LogTM: Log-based transactional memory. In HPCA ’06: Proc. 12th International Symposium on High-Performance Computer Architecture, February 2006, P. – 254-265.

11. Michael F. Spear, Maged M. Michael, and Christoph von Praun. RingSTM: scalable transactions with a single atomic instruction. In SPAA ’08: Proc. 20th Annual Symposium on Parallelism in Algorithms and Architectures, June 2008, P. 275–284.

12. Dave Dice, Ori Shalev, and Nir Shavit. Transactional locking II. In DISC ’06: Proc. 20th International Symposium on Distributed Computing, September 2006. Springer Verlag Lecture Notes in Computer Science volume 4167, P. – 194-208.

13. Pascal Felber, Christof Fetzer, Torvald Riegel. Dynamic performance tuning of word-based software transactional memory. PPOPP 2008. P. – 237-246.

14. Craig Zilles and Ravi Rajwar. Implications of false conflict rate trends for robust software transactional memory. In IISWC ’07: Proc. 2007 IEEE.

15. Olszewski M., Cutler J., Steffan J. G. JudoSTM: A Dynamic Binary-Rewriting Approach to Software Transactional Memory. Proceedings of the 16th International Conference on Parallel Architecture and Compilation Techniques. PACT ’07. 2007. P. 365–375.

16. Intel Corporation. Intel Transactional Memory Compiler and Runtime Application Binary Interface. Revision: 1.0.1, November 2008.


Review

For citations:


Kulagin I., Kurnosov M. Instrumentation and optimization of transactional sections execution in multithreaded programs. Proceedings of the Institute for System Programming of the RAS (Proceedings of ISP RAS). 2015;27(6):135-150. (In Russ.) https://doi.org/10.15514/ISPRAS-2015-27(6)-9



Creative Commons License
This work is licensed under a Creative Commons Attribution 4.0 License.


ISSN 2079-8156 (Print)
ISSN 2220-6426 (Online)