Parallelism reduction method in the high-level VLSI synthesis implementation
Darya Sergeevna ROMANOVA,
Oleg Vladimirovich NEPOMNYASHCHIY,
Igor Nikolayevich RYZHENKO,
Alexander Ivanovich LEGALOV,
Natalya Yurievna SIROTININA https://doi.org/10.15514/ISPRAS-2022-34(1)-5
Abstract
In the article the problems and solutions in the field of ensuring architectural independence and implementation of digital integrated circuits end-to-end design processes are considered. The method and language of parallel programming for functional flow synthesis of design solutions is presented. During the method implementation, the tasks of reducing parallelism and estimating the occupied resources were highlighted. The main feature of the developed method is the introduction of the additional meta-layer into the synthesis process. Algorithms for the parallelism reduction have been developed. The results of software tools development for design support and practical VLSI projects are presented.
Keywords
integrated circuit,
algorithm,
program,
parallel computing model,
high-level synthesis,
functional-stream language
Supporting agencies: The article is based on the materials of the report at the Seventh International Conference «Actual Problems of System and Software Engineering» (APSSE 2021).
About the Authors
Darya Sergeevna ROMANOVA
Siberian Federal University,
Krasnoyarsk State Agrarian University
Russian Federation
Russian Federation
Post-graduate student of the Department of Computer Engineering of the Siberian Federal University, assistant of the Department of IT&MOIS of the Krasnoyarsk State Agrarian University
Oleg Vladimirovich NEPOMNYASHCHIY
Siberian Federal University
Russian Federation
Russian Federation
Professor, Ph.D. in technical sciences, Head of the Computer Science Department at the Siberian Federal University
Igor Nikolayevich RYZHENKO
Siberian Federal University
Assistant Professor at the Computer Science Department
Alexander Ivanovich LEGALOV
National Research University - Higher School of Economics
Russian Federation
Russian Federation
Doctor of Technical Sciences, Professor of the Faculty of Computer Science
Natalya Yurievna SIROTININA
Siberian Federal University
Russian Federation
Russian Federation
Ph.D. in technical sciences, Associate Professor, Department of Computer Science
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Review
For citations:
ROMANOVA D.S., NEPOMNYASHCHIY O.V., RYZHENKO I.N., LEGALOV A.I., SIROTININA N.Yu. Parallelism reduction method in the high-level VLSI synthesis implementation. Proceedings of the Institute for System Programming of the RAS (Proceedings of ISP RAS). 2022;34(1):69-72. https://doi.org/10.15514/ISPRAS-2022-34(1)-5
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